The present invention relates to the field of a synchronous semiconductor memory device, and more particularly to a synchronous semiconductor memory device capable of controlling cell operations by utilizing frequency information of a clock signal.
The synchronous semiconductor memory device is operable without failure even though a high frequency clock signal is inputted thereto since the time of a word line to be disabled and precharged is established in response to frequency information of the clock signal.
A synchronous semiconductor memory device generally synchronizes all of input/output signals with clock signals, and perform for the input/output operation of data by using an input/output register.
The operation of the synchronous semiconductor memory device will be described hereinafter. First, in a read-out operation, at a rising edge of a clock signal, a row address strobe signal /RAS is generated from a chip selection signal /CS, and a row address is admitted to be input into the memory device in response to the /RAS. Then, a word line corresponding to the row address is selected. Further, data of a memory cell connected to the selected word line is loaded on each bit line, and data loaded on the bit line is sensed and amplified by a sense amplifier. A column address is inputted thereto in response to a column address strobe signal /CAS activated at the next rising edge of the clock signal, and the amplified data loaded on a bit line selected by a column decoder is transferred to a data bus. The amplified data on the data bus is stored in the input/output register, and turned out of the memory device in synchronously response to the clock signal CLK.
Meanwhile, in a write-in operation, at a rising edge of a clock signal, the row address strobe signal /RAS is generated from a chip selection signal /CS, and a row address is inputted into the memory device in accordance with an activation of the /RAS. Then, a word line corresponding to the row address is selected. At this time, data is supplied from an external source thereto, and the data stored in an input/output register in synchronism with the clock signal is loaded on a data bus. Further, as a column address is inputted in accordance with a column address strobe signal /CAS activated at the next rising edge of the clock signal, the data on data bus is transferred to the bit line selected by a column decoder. The data transferred to the bit line is stored in a memory cell connected to the selected word line.
With a function of the input/output register, it is possible to control internal operations such as precharging, as synchronized with the clock signal CLK, thereby ensuring a high-speed operation.
Every operation mode of the synchronous semiconductor memory device is setting in accordance with a combination of command signals indicative of states of the operation modes but not predetermined voltage levels of a specific signal. The command signals are conductive synchronously with a clock signal.
Since one operation is executed through several clock cycles, each cycle of the clock signal is assigned to a specific operation state. That is, the operation of the synchronous semiconductor memory device is composed of a plurality of operation states each associated with one of operating cycles of the clock signal. Therefore, in each clock cycle, a finite state machine is necessary to designate a specific state, and the finite state machine receiving input signals /CAS, /RAS, /CS, /WE etc and a clock signal CLK designate a following operation.
If control signals such as the row address strobe signal /RAS and the column address strobe signal /CAS et al are enabled during only one cycle of the clock signal, the operation states are stored in an internal register and the stored operation states are maintained the current input states until new valid address signals are applied thereto. Therefore, an operation state of a chip is determined by combination of the external signals /CS, /RAS, /CAS, and /WE etc applied with much as a pulse width as same as that of the clock signal. The operation state is decoded by a command signal decoder in the chip, and command signals corresponding to the operation state are generated, and thereby chip operations are carried out in response to the command signals.
The read operation will be now explained. At a rising edge of the clock signal, a word line enable command signal ACT and the row address are activated, and a semiconductor memory device sets an active state. At this time, a specific word line is selected by the row address.
Then, if a read command signal and a column address are admitted to be input into the memory cell, the data on the bit line amplified by the sense amplifier is supplied to the data bus, and the data stored in the input/output register in synchronously response to the clock signal CLK is turned out of the memory device.
Here, a time interval between input of the read command signal and output of a valid data is CAS latency CL. The value of the CAS latency CL is established with the integer times of the clock cycle. After the CAS latency CL from input of the read command signal, specified numbers of data are successively generated, and the numbers are equal to a burst length BL. After data as many as the burst length BL is processed, the operation state is automatically established to precharge which is an auto precharge. A generation of an auto prechrge command signal APCG response to a burst end command signal BEND, enters into the auto precharge operation.
The write-in operation will be now explained. At a rising edge of the clock signal, the word line enable command signal ACT and the row address are inputted into the memory device, and the semiconductor memory device is established to an active state. At this time, a specific word line is selected by the row address. Further, if a write command signal and a column address strobe signal are supplied, the data stored in the input/output register in synchronously response to the clock signal CLK is transferred to a data bus, and the data is transferred to a bit line corresponding to the column address, and thereby the data is stored in a memory cell connected to the selected word line.
The precharge state is automatically established by an auto precharge command signal after reading the data as many as burst length BL.
However, in case that a high frequency clock signal is applied, since the read-out and write-in operations are performed in accordance with a cycle set in advance by a parameter, the read-out and write-in operations are progressed when a potential of cell node CN is not high enough. Thus, it is impossible to read out or write in the valid data, thereby to cause to fail cell operations.
The object of the present invention is to prevent a failure in cell operations by setting up a point of time when a word line may be disabled in accordance with the stored frequency information.
Another object of the present invention is to prevent a failure in cell operations by setting up a point of time when a word line man be disabled in accordance with in response to the frequency information corresponding to the detected frequency of the clock signal.
The synchronous semiconductor memory device of the present invention includes a state control circuit for setting up operation states, an address buffer for buffering an inputted address, and a mode register for setting up an operation mode in response to an output signal of the state control circuit and the address of the address buffer. The synchronous semiconductor memory device also includes a frequency information generating circuit and a driving circuit. The frequency information generating circuit detects a frequency of the clock signal in response to the output signal of the state control circuit and the address of the address buffer, and generates frequency information from the frequency of the clock signal. The driving circuit activates a word line in accordance with the output signal of the state control circuit, the output signal of the mode register, and the frequency information of the frequency information generating circuit.